Newsgroups: gnu.utils.help,comp.unix.programmer
> Here is one of targets of my makefile :
> -------------------------
> ttt:
> ifdef AAA
> @echo Yes
> else
> @echo No
> endif
> -------------------------
>
> Can I define the AAA variable *when calling make*
Any variable can be set on the make command line, and that setting takes
precedence over any setting in the makefile (actually, in GNU make
there's a way to overcome that, but not in most makes):
Paul D. Smith
override variable definition
> > also possible :
> >
> > TAG=tag1 make
> > or
> > make TAG=tag1
>
>Since you brought it up...
>
>is it true that the first form can not override variable definition
>in make file whereas the 2nd can? thanks
Generally speaking, yes.
for environment variables, it depends on whether or not you use the "-e"
option to make.
Ken Pizzini
make -e
-e Environment variables override assignments
within makefiles.
Example: File Makefile
TAG = original
test:
[ $${TAG} = tag1 ] && { \
echo "action 1!"; \
}
|
!! |
$ make TAG=tag1
[ ${TAG} = tag1 ] && { \
echo "action 1!"; \
}
action 1!
$ TAG=tag1 make
[ ${TAG} = tag1 ] && { \
echo "action 1!"; \
}
make: *** [test] Error 1
$ TAG=tag1 make -e
[ ${TAG} = tag1 ] && { \
echo "action 1!"; \
}
action 1!
Newsgroups: comp.unix.questions,comp.unix.programmer
> What's the correct way to set/use variables in make?
>
> Or, what's wrong with the following:
>
> test:
> fls=`ls`
> echo aaa $(fls) bbbb
Your "fls" is being set in a subshell, and then the next line invokes
a different subshell, which has no knowledge of the first. To make that
work, you either make fls a _make_ variable, for which all caps is a
usual convention (but only a convention):
test:
echo aaa $(FLS) bbb
Or, if you don't need to access the variable any where else in the
makefile, it's a little more efficient to simply continue the shell
command on another line:
test:
fls=`ls`; \
echo aaa $$(fls) bbb
Note that we need to escape the `$', to prevent "make" from trying to
expand the variable before the shell sees it. With only one `$', it
would likely come out `echo aaa bbb' (unless "fls" were also a make
variable, which is less likely to happen if you stick to the convention
of all caps for make variables.
Frederick
variables in Makefile
use $$fls instead of $$(fls) !
|
|
!! |
right
$ make -f make.pkg
(set -vx; pwd=`pwd`; pwd=`basename $pwd`; cd ..; ls $pwd/* | grep -Ev 'make\.pkg|\.dxt|~' | archh bakfl $pwd -h)
pwd
++ pwd
+ pwd=/home/tong/bin/pf/fileh-1.0
basename $pwd
++ basename /home/tong/bin/pf/fileh-1.0
+ pwd=fileh-1.0
+ cd ..
+ ls fileh-1.0/fdispatch.pm fileh-1.0/fileh.README fileh-1.0/fileh.diz fileh-1.0
wrong
$ make -f make.pkg
(set -vx; pwd=`pwd`; pwd=`basename $(pwd)`; cd ..; ls $(pwd)/* | grep -Ev 'make\.pkg|\.dxt|~' | archh bakfl $(pwd) -h)
pwd
++ pwd
+ pwd=/home/tong/bin/pf/fileh-1.0
basename $(pwd)
pwd
+++ pwd
++ basename /home/tong/bin/pf/fileh-1.0
+ pwd=fileh-1.0
+ cd ..
pwd
++ pwd
+ ls /home/tong/bin/pf/FromText.pm /home/tong/bin/pf/HTML /home/tong/bin/pf/RCS /home/tong/bin/pf/argv_show.pl /home/tong/bin/pf/bibh.pl /home/tong/bin/pf/bt2td
> In /bin/sh (actually, I'm using bash on linux) you can
> do ${PAR:+string} which substitutes 'string' if PAR is set.
> Now i want to do this in a makefile:
> USE_LIB1 = yes
> USE_LIB2 =
> target :
> gcc ........ ${USE_LIB1:+-L$(LIB1_DIR) -llib1} \
> ${USE_LIB2:+-L$(LIB2_DIR) -llib2}
Obviously, as you discovered, you need double-$'s here if you want to
pass $'s in the shell script, rather than have make expand them.
> I can't get this to work. The best I've been able
> to come up with is
> gcc ..... `echo $${USE_LIB1 ....} `
> but that only works if the parameter has been set in the calling
> environment of the makefile, not in the makefile itself.
Most make programs don't export the makefile variables into the
subshells (at least not by default). Since you're on Linux, you're
using GNU make, so you can easily do this. See the GNU make manual and
look up the "export" keyword.
Here's one way:
export USE_LIB1 = yes
export USE_LIB2 =
target:
gcc ... $${USE_LIB1:+-L$(LIB1_DIR) -llib1} \
$${USE_LIB2:+-L$(LIB2_DIR) -llib2}
should work, unless I'm forgetting something. No need for echo, etc.
Of course, it's probably faster and simpler to do all this in make
itself, rather than the shell:
USE_LIB1 = yes
USE_LIB2 =
ifeq ($(USE_LIB1),yes)
LIBS += -L$(LIB1_DIR) -llib1
endif
ifeq ($(USE_LIB2),yes)
LIBS += -L$(LIB2_DIR) -llib2
endif
Paul D. Smith
