Make And Conditions

conditions in Make

Newsgroups: comp.unix.questions

>Can I use conditions in make file?
>
>E.g.:
>
>        [ ${TAG} = tag1 ] && {
>         do this
>         do that
>        }
>
>How can I achive the above behavior?

The action (tab-indented) lines in the file are passed to the shell after a small amount of processing on make's part. To do the above, you need to:

double-up any $'s which are supposed to be interpreted by the shell
end each line of a compound statement with a
pretend that the <\><newline> pair was not there and add semicolons (;s) as needed

you want make to be expanding), then the above example becomes:

[ $${TAG} = tag1 ] && { \
  do this; \
  do that; \
}

just remove one of the $s.)

Ken Pizzini

conditions in Make

Example: File: Makefile

test:
        [ $${TAG} = tag1 ] && { \
          echo "action 1!"; \
          echo "action 2!"; \
          }

$ export TAG=tag1
$ make
[ ${TAG} = tag1 ] && { \
  echo "action 1!"; \
  echo "action 2!"; \
  }
action 1!
action 2!

Conditional Syntax

All instances of conditional syntax are parsed immediately, in their entirety; this includes the `ifdef', `ifeq', `ifndef', and `ifneq' forms.

Makefile and Conditional Arguement Lists

Here is an interesting problem I've stumbled on. I have an application. We are adding support for a new version of a low level third party library. The previous release required me to link against Linux Streams.

Our new prototype system doesn't need Linux Streams. I don't want to have two Makefile for this single discrepency; but if I try to link to Linux Streams on the new prototype, the applications no longer compiles.

Basically, in make, I'd like to call a script (to determine whether I need Linux Streams), and edit my library listing accordingly. I wrote the script easy enough (for this example named isver.sh), but…

ATTEMPT (A)

So, given:

LIBLIST = -ldxxx -ldti -ldl -lsrl

switch : $(OBJECTS)
         ./isver.sh DLGCcom 6 || $(eval LIBLIST += -lLiS)
         gcc $(OBJECTS) $(LIBLIST)  -o switch

RESULT: This looked promising by doesn't work since the eval is not in the Makefile context.

ATTEMPT (B)

The closest I could get was:…

RESULT: This gets the job done but is excruciatingly UGLY!

Makefile and Conditional Arguement Lists

> Q:Does anyone know a better "outside the box" method for accomplishing
> something like this?

$ cat Makefile

LIBLIST := -ldxxx -ldti -ldl -lsrl $(shell ./isver.sh || echo "-lLiS")

all:
        @echo "LIBLIST = $(LIBLIST)"

$ ln -sf /bin/true isver.sh && make
LIBLIST = -ldxxx -ldti -ldl -lsrl
$ ln -sf /bin/false isver.sh && make
LIBLIST = -ldxxx -ldti -ldl -lsrl -lLiS

Or you can make the script itself echo "" or "-lLiS", and simplify the Makefile even more:

LIBLIST := -ldxxx -ldti -ldl -lsrl $(shell ./isver.sh)

Paul Pluzhnikov

Conditional including Make file

Solution

EXTRA_INCLUDES:=$(wildcard makefile.*.mk)
ifneq ($(strip $(EXTRA_INCLUDES)),)
  contents :=  $(shell echo including extra rules $(EXTRA_INCLUDES))
  include $(EXTRA_INCLUDES)
endif

rtf : ${TEX_DEST_DIR}/$(TEX_SOURCE_BASE).rtf
        @printf "== The $@ file '$<' generated\n\n\n"
        echo $(contents)

$ make rtf

== The rtf file '..../file.rtf' generated
echo including extra rules makefile.dep.mk
including extra rules makefile.dep.mk

History

Can't include none-exist files

include makefile.*.mk

Makefile:154: makefile.*.mk: No such file or directory
make: *** No rule to make target `makefile.*.mk'.  Stop.

Including Other Makefiles

The `include' directive tells `make' to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this:

include FILENAMES...

FILENAMES can contain shell file name patterns.

Extra spaces are allowed and ignored at the beginning of the line, but a tab is not allowed. (If the line begins with a tab, it will be considered a command line.) Whitespace is required between `include' and the file names, and between file names; extra whitespace is ignored there and at the end of the directive. A comment starting with `#' is allowed at the end of the line. If the file names contain any variable or function references, they are expanded.

For example, if you have three `.mk' files, `a.mk', `b.mk', and `c.mk', and `$(bar)' expands to `bish bash', then the following expression

include foo *.mk $(bar)

is equivalent to

include foo a.mk b.mk c.mk bish bash

When `make' processes an `include' directive, it suspends reading of the containing makefile and reads from each listed file in turn. When that is finished, `make' resumes reading the makefile in which the directive appears.

The `shell' Function

The `shell' function is unlike any other function except the `wildcard' function (*note The Function `wildcard': Wildcard Function.) in that it communicates with the world outside of `make'.

The `shell' function performs the same function that backquotes (``') perform in most shells: it does "command expansion". This means that it takes an argument that is a shell command and returns the output of the command. The only processing `make' does on the result, before substituting it into the surrounding text, is to convert each newline or carriage-return / newline pair to a single space. It also removes the trailing (carriage-return and) newline, if it's the last thing in the result.

 The commands run by calls to the `shell' function are run when the
function calls are expanded.  In most cases, this is when the makefile
is read in.  The exception is that function calls in the commands of
the rules are expanded when the commands are run, and this applies to
`shell' function calls like all others.

Here are some examples of the use of the `shell' function:

contents := $(shell cat foo)

sets `contents' to the contents of the file `foo', with a space (rather than a newline) separating each line.

files := $(shell echo *.c)

sets `files' to the expansion of `*.c'. Unless `make' is using a very strange shell, this has the same result as `$(wildcard *.c)'.

Conditional Parts of Makefiles

A "conditional" causes part of a makefile to be obeyed or ignored depending on the values of variables. Conditionals can compare the value of one variable to another, or the value of a variable to a constant string. Conditionals control what `make' actually "sees" in the makefile, so they _cannot_ be used to control shell commands at the time of execution.

Example of a Conditional

The following example of a conditional tells `make' to use one set of libraries if the `CC' variable is `gcc', and a different set of libraries otherwise. It works by controlling which of two command lines will be used as the command for a rule. The result is that `CC=gcc' as an argument to `make' changes not only which compiler is used but also which libraries are linked.

libs_for_gcc = -lgnu
normal_libs =

foo: $(objects)
ifeq ($(CC),gcc)
        $(CC) -o foo $(objects) $(libs_for_gcc)
else
        $(CC) -o foo $(objects) $(normal_libs)
endif

Syntax of Conditionals

The syntax of a simple conditional with no `else' is as follows:

CONDITIONAL-DIRECTIVE
TEXT-IF-TRUE
endif

The TEXT-IF-TRUE may be any lines of text, to be considered as part of the makefile if the condition is true. If the condition is false, no text is used instead.

The syntax of a complex conditional is as follows:

CONDITIONAL-DIRECTIVE
TEXT-IF-TRUE
else
TEXT-IF-FALSE
endif

If the condition is true, TEXT-IF-TRUE is used; otherwise, TEXT-IF-FALSE is used instead. The TEXT-IF-FALSE can be any number of lines of text.

The syntax of the CONDITIONAL-DIRECTIVE is the same whether the conditional is simple or complex. There are four different directives that test different conditions. Here is a table of them:

`ifeq (ARG1, ARG2)'
`ifeq 'ARG1' 'ARG2''
`ifeq "ARG1" "ARG2"'
`ifeq "ARG1" 'ARG2''
`ifeq 'ARG1' "ARG2"'

Expand all variable references in ARG1 and ARG2 and compare them.
If they are identical, the TEXT-IF-TRUE is effective; otherwise,
the TEXT-IF-FALSE, if any, is effective.

Often you want to test if a variable has a non-empty value.  When
the value results from complex expansions of variables and
functions, expansions you would consider empty may actually
contain whitespace characters and thus are not seen as empty.
However, you can use the `strip' function (*note Text Functions::)
to avoid interpreting whitespace as a non-empty value.  For
example:

ifeq ($(strip $(foo)),)
TEXT-IF-EMPTY
endif

will evaluate TEXT-IF-EMPTY even if the expansion of `$(foo)'
contains whitespace characters.

`ifneq (ARG1, ARG2)'

Expand all variable references in ARG1 and ARG2 and compare them.
If they are different, the TEXT-IF-TRUE is effective; otherwise,
the TEXT-IF-FALSE, if any, is effective.

`ifdef VARIABLE-NAME'
    If the variable VARIABLE-NAME has a non-empty value, the
    TEXT-IF-TRUE is effective; otherwise, the TEXT-IF-FALSE, if any,
    is effective.  Variables that have never been defined have an
    empty value.

Note that `ifdef' only tests whether a variable has a value.  It
does not expand the variable to see if that value is nonempty.
Consequently, tests using `ifdef' return true for all definitions
except those like `foo ='.  To test for an empty value, use
`ifeq ($(foo),)'.  For example,

bar =
foo = $(bar)
ifdef foo
frobozz = yes
else
frobozz = no
endif

sets `frobozz' to `yes', while:

foo =
ifdef foo
frobozz = yes
else
frobozz = no
endif

sets `frobozz' to `no'.

`ifndef VARIABLE-NAME'
    If the variable VARIABLE-NAME has an empty value, the TEXT-IF-TRUE
    is effective; otherwise, the TEXT-IF-FALSE, if any, is effective.

Extra spaces are allowed and ignored at the beginning of the conditional directive line, but a tab is not allowed. (If the line begins with a tab, it will be considered a command for a rule.) Aside from this, extra spaces or tabs may be inserted with no effect anywhere except within the directive name or within an argument. A comment starting with `#' may appear at the end of the line.

The other two directives that play a part in a conditional are `else' and `endif'. Each of these directives is written as one word, with no arguments. Extra spaces are allowed and ignored at the beginning of the line, and spaces or tabs at the end. A comment starting with `#' may appear at the end of the line.

Conditionals affect which lines of the makefile `make' uses. If the condition is true, `make' reads the lines of the TEXT-IF-TRUE as part of the makefile; if the condition is false, `make' ignores those lines completely. It follows that syntactic units of the makefile, such as rules, may safely be split across the beginning or the end of the conditional.

`make' evaluates conditionals when it reads a makefile. Consequently, you cannot use automatic variables in the tests of conditionals because they are not defined until commands are run (*note Automatic Variables: Automatic.).

To prevent intolerable confusion, it is not permitted to start a conditional in one makefile and end it in another. However, you may write an `include' directive within a conditional, provided you do not attempt to terminate the conditional inside the included file.