> In /bin/sh (actually, I'm using bash on linux) you can
> do ${PAR:+string} which substitutes 'string' if PAR is set.

> Now i want to do this in a makefile:

> USE_LIB1 = yes
> USE_LIB2 =

> target :
>      gcc ........ ${USE_LIB1:+-L$(LIB1_DIR) -llib1} \
>                    ${USE_LIB2:+-L$(LIB2_DIR) -llib2}

Obviously, as you discovered, you need double-$'s here if you want to pass $'s in the shell script, rather than have make expand them.

> I can't get this to work. The best I've been able
> to come up with is

>      gcc ..... `echo $${USE_LIB1 ....} `

> but that only works if the parameter has been set in the calling
> environment of the makefile, not in the makefile itself.

Most make programs don't export the makefile variables into the subshells (at least not by default). Since you're on Linux, you're using GNU make, so you can easily do this. See the GNU make manual and look up the "export" keyword.

Here's one way:

export USE_LIB1 = yes
export USE_LIB2 =

target:
      gcc ... $${USE_LIB1:+-L$(LIB1_DIR) -llib1} \
              $${USE_LIB2:+-L$(LIB2_DIR) -llib2}

should work, unless I'm forgetting something. No need for echo, etc.

Of course, it's probably faster and simpler to do all this in make itself, rather than the shell:

USE_LIB1 = yes
USE_LIB2 =

...

ifeq ($(USE_LIB1),yes)
LIBS += -L$(LIB1_DIR) -llib1
endif
ifeq ($(USE_LIB2),yes)
LIBS += -L$(LIB2_DIR) -llib2
endif

...

target:
      gcc ... $(LIBS)

Paul D. Smith